Early scalable instruction set machine alu status prediction apparatus

ABSTRACT

An apparatus implementing an algorithm for generating carries due to the second instruction of an interlocked instruction pair when executing all combinations of logical as well as arithmetic instruction pairs is developed. The algorithm is then applied to three interlock collapsing ALU means implementations that have been proposed. The critical path for calculating the carries is first presented. Next the expression for generating these carries is used to derive a fast implementation for generating overflow which is implemented in the apparatus. The resulting ALU status determination apparatus includes a three-to-one ALU means for executing plural instructions which can predict the status of three-to-one ALU operations related to the presence/absence of carries incorporated in the three-to-one ALU designed to execute a second instruction of a pair of instructions in parallel and whether or not the second instruction of the pair is independent or dependent on the result of the operation of the first instruction. Additionally, an implementation scheme for predicting result equal to zero is developed for the three-to-one ALU operations.

RELATED APPLICATIONS

This application claims priority and is to be treated as a continuation in part of the following applications:

(1) application Ser. No. 07/504,910, filed Apr. 4, 1990, now U.S. Pat. No. 5,051,940, granted Sep. 24, 1991, entitled "Data Dependency Collapsing Hardware Apparatus", the inventors being Stamatis Vassiliadis et al.;

(2) application Ser. No. 07/619,868 filed Nov. 28, 1990, now U.S. Pat. No. 5,301,341, entitled "Overflow Determination for Three-Operand ALUs in a Scalable Compound Instruction Set Machine", the inventors being Stamatis Vassiliadis et al.;

This application relates to subject matter disclosed in:

(3) application Ser. No. 07/677,079, filed Mar. 29, 1991 now U.S. Pat. No. 5,299,319, entitled "High Performance Interlock Collapsing ALU Apparatus", the inventors being Stamatis Vassiliadis et al., filed concurrently herewith.

Furthermore, the subject matter of this application, while having other applications and uses, may be used in connection with a Scalable Compound Instruction Set Machine (SCISM) as defined by the following additional applications:

(1) application Ser. No. 07/519,382, filed May 4, 1990, entitled "Scalable Compound Instruction Set Machine Architecture", the inventors being Stamatis Vassiliadis et al., abandoned and now continued as U.S. Ser. No. 08/013,982 filed Feb. 5, 1993;

(2) application Ser. No. 07/519,384, filed May 4, 1990, entitled "General Purpose Compound Apparatus For Instruction-Level Parallel Processors", the inventors being Richard J. Eickemeyer et al., abandoned and now continued as U.S. Ser. No. 08/015,272 filed Feb. 5, 1993;

(3) application Ser. No. 07/522,219, filed May 10, 1990, entitled "Compounding Preprocessor For Cache", the inventors being Bartholomew Blaner et al., now issued as U.S. Pat. No. 5,214,763 granted May 25, 1993;

(4) application Ser. No. 07/543,464, filed Jun. 26, 1990, now abandoned entitled "An In-Memory Preprocessor for a Scalable Compound Instruction Set Machine Processor", the inventors being Richard Eickemeyer et al.;

(5) application Serial No. 07/543,458, filed Jun. 26, 1990, now U.S. Pat. No. 5,197,135 entitled "Memory Management for Scalable Compound Instruction Set Machines With In-Memory Compounding", the inventors being Richard Eickemeyer et al., now issued as U.S. Pat. No 5,197,135 granted Mar. 23, 1993;

(6) application Ser. No. 07/642,011, filed Jan. 15, 1991, now U.S. Pat. No. 5,295,249 entitled "Compounding Preprocessor for Cache", the inventors being Bartholomew Blaner et al.;

(3) application Ser. No. 07/677,066, filed Mar. 29, 1991 now abandoned, entitled "System for Compounding Instructions for an Instruction Processor With Different Attributes With Apparatus for Handling Test and Data With Differing Reference Point Information and Backward Compounding Apparatus for Compound Instructions", the inventors being Richard Eickemeyer et al.; and

(3) application Ser. No. 07/677,685, filed Mar. 29, 1991 now U.S. Pat. No. 5,303,356, entitled "System for Preparing Instructions for Instruction Processor and System with Mechanism for Branching in the Middle of a Compound Instruction", the inventors being S. Vassiliadis et al.

These co-pending applications and the present application are owned by one and the same assignee, namely, International Business Machines Corporation of Armonk, N.Y.

FIELD OF THE INVENTION

This invention relates to the field of Arithmetic Logic Units (ALUs), and to a new machine organization which executes pairs of instructions in parallel having "add/logical combinatorial operations" which means combining all four of the following combinations: add-add; add-logical; logical-add; and logical-logical functions, and to a machine organization in which two or more disassociated ALU operations are specified by a single ALU which responds to the parallel issuance of a plurality of separate instructions, each of which specifies ALU operations, and executes the instructions in parallel, and particularly to the prediction of the status for three-to-one arithmetic logic units or ALU's.

BACKGROUND OF THE INVENTIONS

Conventional architectures are scalar, represented by such systems as RISC, IBM System/360 and System/370. In addition there are such devices as have been described in Wulf et al., U.S. Pat. No. 4,819,155 and Oota, U.S. Pat. No. 4,852,040. See also, the article by W. A. Wulf proposed in Computer Architecture News, March, 1988, entitled "The WM Computer Architecture". The Wulf apparatus is for vector processing rather than scalar processing, but teaches two operands are combined in an ALU to produce a result in a first execution cycle, following which the result and a third operand are provide to a second ALU which produces a result in a second execution cycle. This reference hints at pipelining similar to superscalar machines which are known, as one way to improve performance.

Pipelining is a standard technique used by computer designers to improve the performance of computer systems. In pipelining an instruction is partitioned into several steps or stages for which unique hardware is allocated to implement the function assigned to that stage. If the cycle time of an n-stage pipeline implementation is assumed to be m/n, where m is the cycle time of the corresponding implementation not employing pipelining, then the best pipeline implementation will have a cycle time of m/n. Another known technique is super-scalar, which permits instructions, grouped strictly on a first-in-first-out basis to be simultaneously issued. The superscalar machine was not designed for a scalable compound instruction set, where related instructions not necessarily originally written together, may be issued as a plural set unit instruction for execution in parallel.

Parallel execution of instructions has become a popular technique for improving processor performance for a reasonable cost. The invention does not consider the parallel execution of instructions per se as novel, even though parallel execution of base instructions is achieved by the inventions, rather it concerns the prediction of the status of a three-to-one adder. Such an adder may be used in a system which processes instructions in parallel.

It is known to implement a three to one adder. It consists of a three to two carry save adder (CSA) followed by a two to one carry look ahead adder (CLA). S. Vassiliadis and M. Putrino, recognized that the critical path in ALUs is usually limited by determination of result equal to zero. In "Condition code predictor for fixed-point arithmetic units," Int. J. Electronics, vol. 66, no. 6, pp. 887-890, 1989, they proposed a method for predicting that the result is equal to zero for a two-to-one two's complement adder; however, as recognized by the author and one of the joint inventors here, that method does not apply for a three-to-one ALU.

A discussion of one known form of the two-to-one CLA can be found in S. Vassiliadis, "Recursive Equations for Hardware Binary Adders," Int. J. Electronics, vol. 67, no. 2, pp. 201-213, 1989, which discusses hardwired binary adders. This journal article may be referenced for definitions of the known quantities G_(n) ^(x) and T_(n), which represent the pseudo-generate and transmit, respectively, at bit position n in the Boolean expressions which we use to describe the stages of the CLA employed in a described preferred embodiment of our inventions. For ease in understanding of our inventions, they have been precisely detailed in Boolean expressions and the booksets described in the description of our preferred embodiments. In the discussion which follow, only the generation of true logic values of a variable are presented in stage by stage delay. These assumptions, however, are not intended to and do not limit the applicability of the discussion and the devices presented since such a bookset is common in currently available technologies and extendable to other technologies having similar characteristics or equivalent functional power within their bookset.

BACKGROUND OF RELATED INVENTIONS

The System/370 sold by International Business Machines which can be made to execute in parallel certain interlocked instructions, and can perform with limitations the requirements of scalable compound instruction set machine as first disclosed in the referenced applications, and there are such suggestions made in other applications as to possibilities which may be used, for example, application Ser. No. 07/642,011 filed Jan. 16, 1991, now U.S. Pat. No. 5,295,249 as other ALUs for a scalable compound instruction set machine. These existing processors have not been publicly used as such, and there has been no publication of the possibility of such a use, but the possibility has been described in some aspects in applications filed after the priority claimed herein.

Further, by way of background the first collapsing ALU was described in application Ser. No. 07/504,910, now U.S. Pat. No. 5,051,940 filed Apr. 4, 1990, entitled "Data Dependency Collapsing Hardware Apparatus", the inventors being Stamatis Vassiliadis et al; and in application Ser. No. 07/619,868, filed Nov. 28, 1990 now U.S. Pat. No. 5,301,341, entitled "Overflow Determination for Three-Operand ALUs in a Scalable Compound Instruction Set Machine", the inventors being Stamatis Vassiliadis et al., from which this application claims priority. It is the object of this invention to provide new devices for Arithmetic Logic Units (ALUs), and devices which are capable of implementation with an architecture which defines instructions that have an "add/logical combinatorial operation" which means combining all four of the following combinations: add-add; add-logical; logical-add; and logical-logical functions, and to an architecture in which two or more disassociated ALU operations are specified by a single interlock collapsing ALU which responds to the parallel issuance of a plurality of separate instructions, each of which specifies ALU operations, and executes the instructions in parallel. Thus a plurality of separate operands as a feature which the present inventions accommodate are passed to the execution unit (ALU) in the same execution cycle, and they may also be passed altogether with a third operand to the execution unit (ALU). Two results are produced and available at the end of a single execution cycle. One of the results may be produced by the first ALU and another single result may be produced by the second ALU.

Thus, in a data dependency collapsing hardware apparatus, will broadly have an instruction device for receiving a plurality of scalar instructions, a first of which produces a result used by the second of the scalar instructions, and there is a device which simultaneously issues a plurality of operands, at least two of which are used by the first and another of the scalar instructions, and the execution unit, under control signals indicating operations which execute the plurality of scalar instructions, produces in a single cycle a single result corresponding to the performance of the operations on the operands. (See U.S. Ser. No. 07/504,910 referenced above for full details of such a proposed apparatus).

The SCISM architecture is applicable not only to 370 architectures, but other architectures, including RISC, where it is desirable to enhance performance of applications which have been developed and which would desirably operate faster if there were parallel issuance and execution of specified plural instructions for an ALU. Such a system enables new hardware to execute old instructions at a more rapid rate, reducing the necessity of reprogramming old programs for a new machine having a new architecture.

The apparatus for which the disclosures of this application are directed is applicable to parallel execution of instructions, and is specifically advantageous in the environment of the related inventions, and to architectures which issue and execute plural instructions in parallel, such as the Scalable Compound Instruction Set Machine architecture which we now call the SCISM architecture.

Less than ideal speedups have been obtained by parallel execution of instructions partially due to data dependencies also known as interlocks. To reduce this performance degradation, due to interlocks, an interlock collapsing ALU has been provided in U.S. Ser. No. 07/504,910, filed Apr. 4, 1990, now U.S. Pat. No. 5,051,940, and an apparatus for handling all "Add/Logical Combinatorial Operations" has been disclosed in the application noted above for a High Performance Collapsing SCISM ALU. The interlock collapsing ALU would be used in conjunction with a conventional two-to-one ALU in a manner in which the first instruction of an interlocked pair would be executed in the conventional ALU at the same time that both instructions are executed simultaneously in the interlock collapsing ALU. If the instruction pair does not possess an interlock, then the interlock collapsing ALU executes the second instruction singularly as the conventional ALU executes the first instruction.

In addition to producing the correct results, ALU's must also accurately report status. This status can include a report of a less than zero, result greater than zero, result equal to zero, and overflow. For the interlock collapsing ALU, this status should be reported as if the second instruction were executed singularly using the results of the first instruction, as provided by U.S. Ser. No. 07/619,868, filed Nov. 28, 1990 now U.S. Pat. No. 5,301,341. ALU status can be determined if the carries into and from the most significant bit (MSB) are known and result equal to zero can be determined. The determination of result equal zero can at worst be made from the result, if no method of predicting the outcome can be found. Generation of result equal zero using this method would be accurate since for proper operation, the result produced from the interlock collapsing ALU must be identical to the result that would be produced via a serial implementation. Therefore, the problem of generating ALU status in the interlock collapsing ALU can be reduced to that of extracting the carries into and from the MSB that are due to the execution of the second instruction. These carries, which are not explicitly produced during the execution of the interlock collapsing ALU, must be extracted from the information generated during the simultaneous execution of the interlocked instruction pair. An algorithm for extracting these carries during three-to-one add/subtract operations has been provided also by U.S. Ser. No. 07/619,868 filed Nov. 28, 1990, now U.S. Pat No. 5,301,341. Three-to-one add/subtract operations arise from collapsing interlocks between two arithmetic instructions. The algorithm is:

    c.sub.0 =κ.sub.0  λ.sub.0  φ.sub.0

    c.sub.1 =κ.sub.1  λ.sub.1  φ.sub.1

where c₀ and c₁ represent the carries due to the execution of the second operation into and from the MSB, κ₀ and κ₁ represent the carries that would have been produced during the execution of the first instruction, λ₀ and λ₁ represent the carries produced by the carry save adder CSA, and φ₀ and φ₁ represent the carries produced by the carry look-ahead adder CLA used in the three-to-one adder. In this expression, represents a bitwise EXCLUSIVE-OR operation. Thus, an algorithm that can be implemented is known for extracting c₀ and c₁ when the first functional category is executed.

Our own work mentioned above can be improved in the following areas:

1. The systems can be made applicable to all functional categories required to be performed by the three-to-one ALU,

2. Even for the categories to which it is applicable, it will produce critical paths that do not extend the cycle time, and

3. Additional elements and functions can be provided to handle all of the intricacies required for controlling the ALU, which had not been handled heretofore; and where by functional categories is meant:

    ______________________________________                                         A+B+Γ    Arithmetic followed by Arithmetic                               B+(A LOP Γ)                                                                             Logical followed by Arithmetic                                  B LOP (A+Γ)                                                                             Arithmetic followed by Logical                                  B LOP (A LOP Γ).                                                                        Logical followed by Logical                                     ______________________________________                                    

and prior work discusses only the arithmetic followed by arithmetic category.

SUMMARY OF THE INVENTIONS

In this application we present a carry extraction apparatus that accommodates and includes all functional categories. We also provide a means to predict overflow for three-to-one ALU operations. We present result equal zero prediction hardware for the categories; arithmetic followed by arithmetic and logical followed by arithmetic. We prove that the proposed apparatus's will not constitute a critical path when compared to high speed three-to-one ALU's. We provide parallel status determination for three high speed three-to-one ALU's subdivided into two implementation categories.

Our implementations of the preferred embodiment of each of our inventions are detailed in the following detailed description. For a better understanding of the inventions, together with advantages and features, reference may be had to the copending applications for some detailed additional background. Further, specifically as to the improvements described herein reference should be made to the following description and the below-described drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 represents a three-to-one ALU, and a parallel status predictor.

FIG. 2 represents parallel extraction of carries for parallel prediction of status (first embodiment)

FIGS. 3, 3A, and 3B represents parallel extraction of carries for parallel prediction of status (second embodiment)

FIG. 4 represents parallel extraction of overflow for parallel prediction of status (first embodiment)

FIGS. 5, 5A, and 5B represents parallel extraction of overflow for parallel prediction of status (second embodiment)

FIG. 6 represents parallel extraction of result equal zero for parallel prediction of status (all embodiments)

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

To prove the feasibility of the parallel status determination embodiments a fast ALU implementation must be assumed as a basis for making a comparison of the critical paths. We assume the fastest three-to-one ALU implementations known to us, i.e. as provided by the apparatus disclosed by U.S. Ser. No. 07/677,079, filed Mar. 29, 1991, now U.S. Pat. No. 5,299,319, filed concurrently herewith, and included herein by reference as noted above. To describe our invention, we illustrate our invention by disclosure of equations which provide the implementation of our preferred embodiment of our various inventions, as implementations of the embodiments, each of which may be commonly known as a scheme or schema.

Carry Extraction for the First Implementation Scheme

In this implementation scheme, the carry from the CSA at bit position i is:

    λ.sub.i =α.sub.i β.sub.i +α.sub.i γ.sub.i +β.sub.i γ.sub.i

where α_(i), β_(i), and γ_(i) represent the inputs into the CSA corresponding to the inputs of the ALU, A_(i), B_(i), and Γ_(i), respectively. In this equation, + represents bitwise OR, and juxtaposition represents bitwise AND. The inputs A and Γ contain the operands for the first instruction while the input B contains the independent operand for the second interlocked instruction. All inputs to the CSA can be forced to zero or fed the corresponding input as shown in FIG. 1.

First consider a three-to-one addition. For this case, the CSA carry is:

    λ.sub.i =A.sub.i B.sub.i +A.sub.i Γ.sub.i +B.sub.i Γ.sub.i,

the appropriate CSA carry for a three-to-two addition as desired by the above carry extraction algorithm. In addition the carry at bit position i due to the first instruction can be generated from the CSA inputs α_(i) and γ_(i). Using CLA techniques, this carry at bit positions 0 and 1, κ₀ and κ₁, can be generated in three stages using the assumed bookset as follows:

STAGE 1 ##EQU1##

STAGE 2 ##EQU2##

STAGE 3

    κ.sub.0 =T.sub.0 G.sub.0.sup.*7 +T.sub.0 T.sub.1.sup.8 G.sub.8.sup.*15 +T.sub.0 T.sub.1.sup.16 G.sub.16.sup.*23 +T.sub.0 T.sub.1.sup.24 Ψ.sub.24.sup.30

    κ.sub.1 =T.sub.1 G.sub.1.sup.*7 +T.sub.1.sup.8 G.sub.8.sup.*15 +T.sub.1.sup.16 G.sub.16.sup.*23 +T.sub.1.sup.24 Ψ.sub.24.sup.30.

In these expressions, G_(n) ^(*m), T_(n) ^(m), and Ψ_(n) ^(m) represent the pseudo-propagate, transmit and new carry, respectively, from bit position m to bit position n, while G_(n) * and T_(n) represent the pseudo-generate and transmit, respectively, at bit position n. Definitions of these quantities can be found in Int. J. Elec. Vol. 67, No. 2, supra. Also, τ₂ represents the hot one that would have been supplied during the execution of the first instruction. A set of requirements for τ₂ that are sufficient, though maybe not necessary, to produce valid results for the three-to-one add/subtract operations has been given in U.S. Ser. No. 07/619,868 filed Nov. 28, 1990, supra. These requirements can be summarized as:

(1) if two hot ones are supplied to the three-to-one ALU, then τ₂ =1;

(2) if no hot ones are supplied to the three-to-one ALU, then τ₂ =0;

(3) if adding/subtracting a third operand with the result of a logical operation, then τ₂ =0.

The above logical expressions produce zero for both κ₀ and κ₁ when the second functional category is executed. This result follows since both α and γ are forced to zero when executing this functional category. With α and γ both zero, all of the pseudo-generates and transmits will be zero. In addition, since τ₂ is zero, the new carry's, Ψ_(i) 's are all zero. Thus, all of the literals in the expressions for κ₀ and κ₁ are zero so that the results will be zero. With κ₀ and κ₁ both zero and since λ₀ and λ₁ are both zero as noted above, the algorithm for extracting the carries, c₀ and c₁ reduce to:

    c.sub.0 =O O φ.sub.0 =φ.sub.0

    c.sub.1 =O O φ.sub.1 =φ.sub.1.

Thus, the extracted carries equal the carries from the CLA as desired.

Extraction of carries due to the second instruction of a compound instruction pair is required only for the first two functional categories as was discussed in the Background of Related Inventions section specifically regarding U.S. Ser. No. 07/619,868, supra.

The stage-by-stage implementation for generating κ₀ and κ₁ was given above. To this implementation the expressions leading to λ₀, λ₁, φ₀, φ₁, and ultimately to c₀ and c₁ must be added to complete the implementation for generating c₀ and c₁. A stage-by-stage description for the first implementation scheme is given below. In this description, pseudo-generates and transmits for generating κ₀ and κ₁ have been subscripted with a cc (carry correct) to distinguish them from the pseudo-generates and transmits of the CLA used in the three-to-one add/subtract by which φ₀ and φ₁ are generated. The expressions at each stage are:

STAGE 1 ##EQU3##

STAGE 2 ##EQU4##

STAGE 3 ##EQU5##

STAGE 4

    κ.sub.0 *=κ.sub.0  λ.sub.0

    κ.sub.1 *=κ.sub.1  λ.sub.1

    φ.sub.1 =T.sub.1 G.sub.1.sup.*8 +T.sub.1 T.sub.2.sup.9 G.sub.9.sup.*16 +T.sub.1 T.sub.2.sup.17 G.sub.17.sup.*24 +T.sub.1 T.sub.2.sup.25 Φ.sub.25.sup.31

STAGE 5

    c.sub.1 =κ.sub.1 * φ.sub.1

    c.sub.0 =κ.sub.0 *T.sub.0 +κ.sub.0 *G.sub.0 φ.sub.1 +κ.sub.0 *G.sub.0 +κ.sub.0 *T.sub.0 φ.sub.1.

All of the above expressions, except that for the calculation of c₀ follow from a direct application of the algorithm for extracting carries due to the second instruction or from the recursive equations for hardwired binary adders as discussed in Int. J. Elec. Vol. 67, No. 2, supra. The expression for c₀ can be derived as follows. The expression for c₀ is: ##EQU6##

But, φ₀ can be expressed as:

    φ.sub.0 =T.sub.0 Φ.sub.0.

Substituting the expression for Φ₀ :

    Φ.sub.0 =G.sub.0 *+T.sub.1 Φ.sub.1

into the expression for φ₀ produces: ##EQU7##

Recognizing that T₁ Φ₁ is φ₁ allows φ₀ to be written as:

    φ.sub.0 =T.sub.0 G.sub.0 *+T.sub.0 φ.sub.1.

This expression for φ₀ can now be substituted into the expression for generating c_(o) to give:

    c.sub.0 =κ.sub.0 * (T.sub.0 G.sub.0 *+T.sub.0 φ.sub.1).

Expanding the above expression into the canonical sum of products for EXCLUSIVE-OR produces: ##EQU8##

But T₀ G₀ * can be reduced to: ##EQU9##

Substituting this into the expression for c₀ yields:

    c.sub.0 =κ.sub.0 *T.sub.0 +κ.sub.0 *G.sub.0 *φ.sub.1 +κ.sub.0 *G.sub.0 *+κ.sub.0 *T.sub.0 φ.sub.1

which is the expression used in the five stage implementation. Thus, both c₀ and c₁ can be generated in five stages with the assumed bookset for this implementation scheme. The logic diagram for the generation of c₀ and c₁ for the first implementation scheme are depicted in FIG. 2.

Carry Extraction for the Second Implementation Scheme

Complications arise when attempting to apply the carry extraction algorithm to the second scheme for implementing the SCISM ALU. These complications arise because λ_(i) and κ_(i) are not guaranteed to be a logic zero when a three-to-one addition is not desired. For example, the CSA carry for this implementation is computed by U.S. Ser. No. 07/504,910, supra.: ##EQU10##

For this implementation to execute the second functional category, it is required that λ_(i) be equal to B_(i-1) when 1≦i≦32. This can be achieved by making Ω₁, Ω₂, and τ₂ a logic zero while making Ω₃ a logic one. Therefore, λ_(i) takes on the value of the ALU input, B_(i-1). Consequently, λ_(i) can not be guaranteed to be a logic zero for 1≦i≦32. Similarly, κ_(i) can not be guaranteed to be a logic zero since the operands corresponding to the first instruction are not forced to a logic zero. Because of these results, controls must be added to the implementation of the carry extraction algorithm to extract the desired carry as if λ_(i) and κ_(i) were logic zero, but allow λ_(i) and κ₁ to be used as generated when extracting the carries due to a three-to-one add/subtract.

The complication due to λ_(i) not being a logic zero when it is not utilized can be overcome by producing a conventional CSA carry that is gated by a control signal indicating that the operation being executed is a three-to-one add/subtract. This signal must only control the carries generated at the bit positions zero and one as these are the only positions at which the carries due to the second operation need to be extracted for generating ALU status. These additional carry signals, denoted as λ_(cc0) and λ_(cc1), are generated as:

    λ.sub.cc0 =Ω.sub.3 to 1 α.sub.0 β.sub.0 +Ω.sub.3 to 1 α.sub.0 γ.sub.0 +Ω.sub.3 to 1 β.sub.0 γ.sub.0

    λ.sub.cc1 =Ω.sub.3 to 1 α.sub.1 β.sub.1 +Ω.sub.3 to 1 α.sub.1 γ.sub.1 +Ω.sub.3 to 1 β.sub.1 γ.sub.1

where Ω₃ to 1 is the control signal and is a logic one if a three-to-one addition/subtraction is being executed. These extra carry signals have the desired property of being the CSA carry when a three-to-one add/subtract is being executed but being a logic zero otherwise; therefore, they can be substituted into the carry extraction algorithm for λ₀ and λ₁ when extracting c₀ and c₁. The complication of κ₁ not being a logic zero when not being utilized can be overcome by considering the third stage in the generation of κ₀ and κ₁. In this stage, these quantities are produced by the expressions:

    κ.sub.0 =T.sub.0 G.sub.0.sup.*7 +T.sub.0 T.sub.1.sup.8 G.sub.8.sup.*15 +T.sub.0 T.sub.1.sup.16 G.sub.16.sup.*23 +T.sub.0 T.sub.1.sup.24 Ψ.sub.24.sup.30

    κ.sub.1 =T.sub.1 G.sub.1.sup.*7 +T.sub.1.sup.8 G.sub.8.sup.*15 +T.sub.1.sup.16 G.sub.16.sup.*23 +T.sub.1.sup.24 Ψ.sub.24.sup.30.

Since the expression for κ₁ is directly implemented in the assumed bookset by a 2×4 AO book, the gating control signal indicating that a three-to-one add/subtract operation is being executed can be directly applied resulting in a 3×4 AO book. Thus, κ₁, can be produced by:

    κ.sub.1 =Ω.sub.3 to 1 T.sub.1 G.sub.1.sup.*7 +Ω.sub.3 to 1 T.sub.1.sup.8 G.sub.8.sup.*15 +Ω.sub.3 t1 T.sub.1.sup.16 G.sub.16.sup.*23 +Ω.sub.3 to 1 T.sub.1.sup.24 Ψ.sub.24.sup.30.

This signal has the desired qualities of being zero when a three-to-one add/subtract operation is not specified but being the carry produced into the MSB during the execution of the first instruction when a three-to-one add/subtract operation is specified. A first glance at the expression for generating κ₀ is discouraging for using a similar approach since the expression for generating κ₀ already requires a 3×4 AO book. However, the expression for the literal, T₀, which can be generated in the first stage, is:

    T.sub.0 =α.sub.0 +γ.sub.0.

This expression requires a two-way OR book to which a gating signal can be added resulting in a 2×2 AO book. The gated T₀, denoted as T₀ *, therefore, can be generated in the first stage and substituted for T₀ in the third stage expression for generating κ₀. The results are:

STAGE 1 ##EQU11##

STAGE 2 ##EQU12##

STAGE 3

    κ.sub.0 =T.sub.0 *G.sub.0.sup.*7 +T.sub.0 * T.sub.1.sup.8 G.sub.8.sup.*15 +T.sub.0 *T.sub.1.sup.16 G.sub.16.sup.*23 +T.sub.0 *T.sub.1.sup.24 Ψ.sub.24.sup.30

    κ.sub.1 =Ω.sub.3 to 1 T.sub.1 G.sub.1.sup.*7 +Ω.sub.3 to 1 T.sub.1.sup.8 G.sub.8.sup.*15 +Ω.sub.3 t1 T.sub.1.sup.16 G.sub.16.sup.*23 +Ω.sub.3 to 1 T.sub.1.sup.24 Ψ.sub.24.sup.30.

Both κ₀ and κ₁ generated in this manner have the desired property of being the carry due to the execution of the first instruction when executing a three-to-one add/subtract but being a logic zero otherwise.

From the above results, c₀ and c₁ can be determined by:

    c.sub.0 =κ.sub.0  λ.sub.cc0  φ.sub.0

    c.sub.1 =κ.sub.1  λ.sub.cc1  φ.sub.1

where κ₀ and κ₁ are generated as just described. No additional restrictions have been placed on supplying hot ones to the ALU for this technique.

Both c₀ and c₁ can be generated in five stages for this implementation scheme; therefore, no additional delay results from the implementation. A stage-by-stage description of the carry extraction follows. As for the description for the first implementation scheme, the pseudo-generates and transmits associated with generating κ₀ and κ₁ have been subscripted with cc to distinguish them from their counterparts for executing the three-to-one add. The stage-by-stage implementation is:

STAGE 1 ##EQU13##

STAGE 2 ##EQU14##

STAGE 3 ##EQU15##

STAGE 4

    κ.sub.0 *=κ.sub.0  λ.sub.cc0

    κ.sub.1 *=κ.sub.1  λ.sub.cc1

    φ.sub.1 =T.sub.1 G.sub.1.sup.*8 +T.sub.1 T.sub.2.sup.9 G.sub.9.sup.*16 +T.sub.1 T.sub.2.sup.17 G.sub.17.sup.*24 +T.sub.1 T.sub.2.sup.25 Φ.sub.25.sup.31

STAGE 5

    c.sub.1 =κ.sub.1 * φ.sub.1

    C.sub.0 =κ.sub.0 *T.sub.0 +κ.sub.0 *G.sub.0 *φ.sub.1 +κ.sub.0 *G.sub.0 *+κ.sub.0 *T.sub.0 φ.sub.1.

All of the expressions in the above implementation for extracting the carries from the second instruction can be implemented with the assumed bookset except for the transmit generated across three bit positions, T_(i) ^(i+2), which occurs in Stage 2. This transmit is needed to produce φ₁ in the fourth stage which is then used to determine c₀ and c₁ in the fifth stage. If the generation of this transmit is to be avoided, c₀ and c₁ must be generated without the explicit generation of φ₁.

To generate c₀ and c₁ without explicitly generating φ₁, φ₁ must be expanded using the recursive equations. Such an expansion gives: ##EQU16##

Substituting this expression for φ₁ into the expressions for c₀ and c₁ in Stage 5 gives:

    c.sub.0 =κ.sub.0 *T.sub.0 +κ.sub.0 *G.sub.0 *(T.sub.1 G.sub.1.sup.*x +T.sub.1 T.sub.2.sup.x+1 Φ.sub.x+1.sup.y)

     κ.sub.0 *G.sub.0 * + κ.sub.0 *T.sub.0 (T.sub.1 G.sub.1.sup.*x

     +T.sub.1 T.sub.2.sup.x+1 Φ.sub.x+1.sup.y)

    c.sub.1 =κ.sub.1 * (T.sub.1 G.sub.1.sup.*x +T.sub.1 T.sub.2.sup.x+1 Φ.sub.x+1.sup.y).

The expression for c₁ can be developed using standard Boolean techniques as follows. ##EQU17##

This expression for c₁ can be generated in the fifth stage using the assumed bookset if:

    T.sub.1 +T.sub.2.sup.x+1 G.sub.1.sup.*x

    G.sub.1.sup.*x

    G.sub.1.sup.*x

    Φ.sub.x+1.sup.y

    Φ.sub.x+1.sup.y

can be generated in the fourth stage.

Now consider the expression for c₀. This expression can be developed using standard Boolean techniques as follows. ##EQU18##

This last expression can be used to generate c₀ in the fifth stage using the assumed bookset if, in addition to those values required for generating c₁, the following values are generated in the fourth stage:

    T.sub.0 +G.sub.0 *T.sub.1 +T.sub.2.sup.x+1 G.sub.0 *G.sub.1.sup.*x

    G.sub.0 *T.sub.0.sup.1 G.sub.1.sup.*x

    G.sub.0 *G.sub.1.sup.*x

    T.sub.0.sup.x+1.

To determine whether the above signals can be generated by the fourth stage of the implementation, the values for x and y in the expressions, Φ_(x+1) ^(y) and G₁ ^(*x), must be determined. These values are determined by the number of bit positions that can be spanned in three stages for the new carry, Φ_(n) ^(m), using the assumed bookset. By application of the recursive equations for binary adders, the number of bit positions that can be spanned for the assumed bookset is:

STAGE 1

Generate results for CSA and Logic function block as shown above

STAGE 2 ##EQU19##

STAGE 3 ##EQU20##

STAGE 4

    Φ.sub.9.sup.26 =G.sub.9.sup.*14 +T.sub.10.sup.11 T.sub.12.sup.15 G.sub.15.sup.*20 +T.sub.10.sup.11 T.sub.12.sup.21 G.sub.21.sup.*26

     +T.sub.10.sup.11 T.sub.12.sup.27 Φ.sub.27.sup.31

from which x can be determined to be eight, and y to be 26. Substituting these values into the expressions that must be generated by the fourth stage provides the requirements for generating c₀ and c₁ in five stages with the assumed bookset. These requirements are the generation of:

    T.sub.1 +T.sub.2.sup.9 G.sub.1.sup.*8

    G.sub.1.sup.*8

    T.sub.1.sup.9

    G.sub.1.sup.*8

    T.sub.0 +G.sub.0 *T.sub.1 +T.sub.2.sup.9 G.sub.0 *G.sub.1.sup.*8

    G.sub.0 *+T.sub.0.sup.1 G.sub.1.sup.*8

    G.sub.0 *

    T.sub.0.sup.9

by the fourth stage in addition to that of Φ₉ ²⁶. Φ₉ ²⁶ can be generated in the fourth stage as shown above; the remaining expressions can also be generated by the fourth stage by:

STAGE 1

Generate results for CSA and Logic function block as shown above

STAGE 2 ##EQU21##

STAGE 3 ##EQU22##

STAGE 4

    G.sub.1.sup.*8 =G.sub.1.sup.*2 +T.sub.2.sup.3 G.sub.3.sup.*8

    G.sub.1.sup.*8 =G.sub.1.sup.*2 +T.sub.2.sup.3 G.sub.3.sup.*8 =G.sub.1.sup.*2 T.sub.2.sup.3 +G.sub.1.sup.*2 G.sub.3.sup.*8

    u.sub.2 =T.sub.1 +T.sub.2.sup.9 G.sub.1.sup.*8 =T.sub.1 +T.sub.2.sup.9 G.sub.1.sup.*2 T.sub.2.sup.3

     +T.sub.2.sup.9 G.sub.1.sup.*2 G.sub.3.sup.*8 =T.sub.1 +T.sub.2.sup.3 G.sub.1.sup.*2 +T.sub.2.sup.9 G.sub.1.sup.*2 G.sub.3.sup.*8

    U.sub.3 =G.sub.0 *+T.sub.0.sup.1 G.sub.1.sup.*8 =G.sub.0 *+T.sub.0.sup.1 (G.sub.1.sup.*2 +T.sub.2.sup.3 G.sub.3.sup.*8)

     =G.sub.0 *+T.sub.0.sup.1 G.sub.1.sup.*2 +T.sub.0.sup.1 T.sub.2.sup.3 G.sub.3.sup.*8

    u.sub.4 =T.sub.0 +G.sub.0 *T.sub.1 +T.sub.2.sup.9 G.sub.0 *G.sub.1.sup.*8 =T.sub.0 +G.sub.0 *T.sub.1

     +T.sub.2.sup.9 G.sub.0 *(G.sub.1.sup.*2 T.sub.2.sup.3 + G.sub.1.sup.*2 G.sub.3.sup.*8)=T.sub.0 +G.sub.0 *T.sub.1

     +T.sub.2.sup.3 u.sub.1 +T.sub.2.sup.9 u.sub.1 G.sub.3.sup.*8

From the above considerations, the stage by stage implementation for generating c₀ and c₁ in five stages is:

STAGE 1 ##EQU23##

STAGE 2 ##EQU24##

STAGE 3 ##EQU25##

STAGE 4

    κ.sub.0 *=κ.sub.0  λ.sub.cc0

    κ.sub.1 *=κ.sub.1  λ.sub.cc1

    G.sub.1.sup.*8 =G.sub.1.sup.*2 +T.sub.2.sup.3 G.sub.3.sup.*8

    G.sub.1.sup.*8 =G.sub.1.sup.*2 T.sub.2.sup.3 +G.sub.1.sup.*2 G.sub.3.sup.*8

    U.sub.2 =T.sub.1 +T.sub.2.sup.3 G.sub.1.sup.*2 +T.sub.2.sup.9 G.sub.1.sup.*2 G.sub.3.sup.*8

    U.sub.3 =G.sub.0 *+T.sub.0.sup.1 G.sub.1.sup.*2 +T.sub.0.sup.1 T.sub.2.sup.3 G.sub.3.sup.*8

    U.sub.4 =T.sub.0 +G.sub.0 *T.sub.1 +T.sub.2.sup.3 U.sub.1 +T.sub.2.sup.9 U.sub.1 G.sub.3.sup.*8

    Φ.sub.9.sup.26 =G.sub.9.sup.*14 +T.sub.10.sup.11 T.sub.12.sup.15 G.sub.15.sup.*20 +T.sub.10.sup.11 T.sub.12.sup.21 G.sub.21.sup.*26 +T.sub.10.sup.11 T.sub.12.sup.27 Φ.sub.27.sup.31

STAGE 5

    c.sub.1 =κ.sub.1 *U.sub.2 +κ.sub.1 *T.sub.1 G.sub.1.sup.*8 +κ.sub.1 *T.sub.1.sup.9 Φ.sub.9.sup.26 +κ.sub.1 *G.sub.1.sup.*8 Φ.sub.9.sup.26

    c.sub.0 =κ.sub.0 *U.sub.4 +κ.sub.0 *U.sub.3 +κ.sub.0 *U.sub.1 Φ.sub.9.sup.26 +κ.sub.0 *T.sub.0.sup.9 Φ.sub.9.sup.26.

The logic diagram for the generation of c₀ and c₁ for the second implementation scheme are depicted in FIG. 3.

Generation of Overflow

In the previous section, the implementation for extracting carries due to the execution of only the second of an interlocked pair of instructions was presented for the two ALU implementation schemes. The carries into and out of the MSB were shown to be calculable in five stages using the assumed bookset. It is well known that arithmetic overflow can be determined for two's complement addition by the EXCLUSIVE-OR between the carry into and out of the MSB. Therefore, overflow due only to the execution of the second instruction can be produced from the EXCLUSIVE-OR between c₀ and c₁. Using this approach, overflow can be generated in six stages of the assumed bookset since c₀ and c₁ are generated in five. This would result in the critical path for the ALU. In this section, an earlier generation of overflow is pursued. First, developments that are common to both implementation schemes are presented. Next the first implementation scheme is considered with an implementation for the assumed bookset presented. Finally, the implementation for the second ALU implementation scheme is developed.

From the signals described in the previous section, overflow can be computed explicitly by:

    OF=κ.sub.0  κ.sub.1  λ.sub.cc0  λ.sub.cc1 φ.sub.0  φ.sub.1.

The EXCLUSIVE-OR of two carries in a binary adder, Φ₀ and Φ₁ using a conventional CLA is equal to:

    θ.sub.0  θ.sub.1 =T.sub.0 θ.sub.1 +G.sub.0 *θ.sub.1.

These results are directly applicable to the EXCLUSIVE-OR between κ₀ and κ₁ because they are derived by an implicit, conventional CLA, but the results are not directly applicable to the EXCLUSIVE-OR between φ₀ and φ₁ since the inputs to the CLA producing them have been modified. Thus, κ₀ κ₁ can be expressed as:

    κ.sub.0  κ.sub.1 =T.sub.cc0 κ.sub.1 +G.sub.cc0 *κ.sub.1,

but a more general expression must be used for expressing φ₀ φ₁. To develop this expression, φ₀ needs to be expressed in terms of φ₁. Given (according to Int. J. Elec. Vol. 67, No. 2, supra) that:

    φ.sub.0 =T.sub.0 G.sub.0 *+T.sub.0 φ.sub.1,

    φ.sub.0  φ.sub.1 =(T.sub.0 G.sub.0 *+T.sub.0 φ.sub.1) φ.sub.1.

Expanding the EXCLUSIVE-OR into its canonical sum of products yields: ##EQU26##

Further development of these expressions to derive an expression for overflow is contingent upon the ALU implementation being considered since the expressions for λ_(cc0), λ_(cc1), T₀ and G₀ * differ for the two implementation schemes. The expression for overflow for each of these schemes is developed below. Before deriving these expressions, the following theorem, which will be useful in the derivations, is proven:

Theorem 1

If a, b, c, and d are Boolean variables, then

    (abd+abd) c=(ab+ab)d (ac+bc+abc)

Proof: ##EQU27##

Generation of Overflow for the First Implementation Scheme

In this implementation scheme, λ_(cc0) is equivalent to λ₀. Therefore, ##EQU28##

Substituting this result into the expression for overflow produces:

    OF=((α.sub.0  γ.sub.0)κ.sub.1) (β.sub.0 (α.sub.0  γ.sub.0)) λ.sub.cc1  φ.sub.0 φ.sub.1.

Now consider φ₀ φ₁. From the above developments, this can be expressed as:

    φ.sub.0  φ.sub.1 =T.sub.0 φ.sub.1 +T.sub.0 G.sub.0 *φ.sub.1

Since the inputs to the CLA for this implementation scheme have been modified so that one of the inputs is fed the carry from the CSA and the output of the logic function block from which it must select the appropriate signal while the other input is fed the sum, the expressions for T₀ and G₀ * will differ from those for a conventional CLA. The expressions for these signals for this implementation scheme at bit position 0 are:

    T.sub.0 =σ.sub.0 +λ.sub.1 L.sub.0

    G.sub.0 *=σ.sub.0 (λ.sub.1 +L.sub.0).

Substituting these expressions into the expression for φ₀ φ₁ produces: ##EQU29##

Since λ_(cc1) is equal to λ₁, φ₀ φ₁ λ_(cc1) can be expressed as: ##EQU30##

Thus by theorem 1: ##EQU31##

Substituting this expression into that for generating overflow gives:

    OF=(α.sub.0  γ.sub.0)κ.sub.1  β.sub.0 (α.sub.0  γ.sub.0) (σ.sub.0 λ.sub.1

     +σ.sub.0 L.sub.0) (σ.sub.0 L.sub.0 λ.sub.1 +σ.sub.0 λ.sub.1 +σ.sub.0 L.sub.0)φ.sub.1.

Expressing overflow in this manner allows it to be calculable in five stages. The calculation proceeds stage by stage as follows:

STAGE 1

    X.sub.1 =α.sub.0  γ.sub.0

    X.sub.2 =β.sub.0 (α.sub.0  γ.sub.0)=β.sub.0 α.sub.0 γ.sub.0 +β.sub.0 α.sub.0 γ.sub.0

STAGE 2

    X.sub.3 =σ.sub.0 λ.sub.1 +σ.sub.0 L.sub.0

    X.sub.4 =σ.sub.0 L.sub.0 λ.sub.1 +σ.sub.0 λ.sub.1 +σ.sub.0 L.sub.0

STAGE 3

    X.sub.5 =X.sub.2  X.sub.3

    κ.sub.1 =T.sub.cc1 G.sub.cc1.sup.*7 +T.sub.cc1.sup.8 G.sub.cc8.sup.*15 +T.sub.cc1.sup.16 G.sub.cc16.sup.*23 +T.sub.cc1.sup.24 Ψ.sub.24.sup.30

STAGE 4

    X.sub.6 =X.sub.5  X.sub.1 κ.sub.1 =X.sub.5 X.sub.1 +X.sub.5 κ.sub.1 +X.sub.5 X.sub.1 κ.sub.1

    φ.sub.1 =T.sub.1 G.sub.1.sup.*8 +T.sub.1 T.sub.2.sup.9 G.sub.9.sup.*16 +T.sub.1 T.sub.2.sup.17 G.sub.17.sup.*24 +T.sub.1 T.sub.2.sup.25 Φ.sub.25.sup.31

STAGE 5

    OF=X.sub.6  X.sub.4 φ.sub.1 =X.sub.6 X.sub.4 φ.sub.1 +X.sub.6 X.sub.4 +X.sub.6 φ.sub.1.

The logic diagram for the computation of overflow for the first implementation scheme is depicted in FIG. 4. For simplicity, the expressions for generating κ₁ and φ₁ are given during the appropriate stage in the stage by stage description without showing the generation of their precursors. The details of the stage by stage generation of these values, can be found in the section called "Carry Extraction for the First Implementation Scheme".

Generation of Overflow for the Second Implementation Scheme

In the second implementation scheme, λ_(cc0) and λ_(cc1) can be expressed in terms of λ₀ and λ₁ as:

    λ.sub.cc0 =Ω.sub.3 to 1 λ.sub.0

    λ.sub.cc1 =Ω.sub.3 to 1 λ.sub.1.

In addition, the carries produced due to the first operation, κ₀ and κ₁ are generated by gating the corresponding expressions with a signal indicating that a three-to-one addition is being executed. Let the ungated signals be designated as κ₀ and κ₁. Then κ₀ and κ₁ can be expressed as:

    κ.sub.0 =Ω.sub.3 to 1 κ.sub.0

    κ.sub.1 =Ω.sub.3 to 1 κ.sub.1.

Using this notation, overflow can be expressed as: ##EQU32##

Since.

    AB AD=A(B D),

    OF=[Ω.sub.3 to 1 (κ.sub.0  κ.sub.1  λ.sub.0)] λ.sub.cc1  φ.sub.0  φ.sub.1.

Making use of the expression for κ₀ κ₁ λ₀ and using the assumed terminology gives:

    κ.sub.0  κ.sub.1  λ.sub.0 =(α.sub.0 γ.sub.0)κ.sub.1  β.sub.0 (α.sub.0  γ.sub.0),

so that: ##EQU33##

Now consider the expression φ₀ φ₁, which, from above, can be expressed as:

    φ.sub.0  φ.sub.1 =T.sub.0 φ.sub.1 +T.sub.0 G.sub.0 *φ.sub.1.

As for the first implementation scheme, the pseudo-generate and transmit at bit position 0 differ from those of a conventional CLA since the inputs to the CLA have been modified in this implementation. The expression for these values is from U.S. Pat. No. 5,299,319 Phillips et al., supra.:

    T.sub.0 =λ.sub.1 +Ω.sub.4 σ.sub.0 +L.sub.0

    G.sub.0 *=Ω.sub.4 λ.sub.1 σ.sub.0 +λ.sub.1 L.sub.0

where Ω₄ is a control signal to zero the sum from the CSA when it is not required to execute the specified function. Substituting these into the expression for φ₀ φ₁ yields: ##EQU34##

Therefore, φ₀ φ₁ λ_(cc1) can be expressed as:

    φ.sub.0  φ.sub.1  λ.sub.cc1 =[λ.sub.1 (Ω.sub.4 σ.sub.0 +L.sub.0)φ.sub.1 +λ.sub.1 (Ω.sub.4 σ.sub.0 +L.sub.0)φ.sub.1 ] λ.sub.cc1.

Let,

    ν=Ω.sub.4 σ.sub.0 +L.sub.0,

then by theorem 1: ##EQU35## so that:

    φ.sub.0  φ.sub.1  λ.sub.cc1 =[(λ.sub.1 ν)φ.sub.1 ] (λ.sub.1 λ.sub.cc1 +λ.sub.cc1 ν+λ.sub.1 λ.sub.cc1 ν).

Substituting this expression into that for overflow gives: ##EQU36##

In the section called "Carry Extraction for the Second Implementation Scheme" it was shown that φ₁ can not be generated in four stages using the assumed bookset for this implementation scheme. Thus, if overflow is to be implemented in five stages, it must be implemented without the explicit calculation of φ₁. Also in "Carry Extraction for Second Implementation Scheme" the expression for φ₁ that could be available by the fifth stage was:

    φ.sub.1 =T.sub.1 G.sub.1.sup.*8 +T.sub.1 T.sub.2.sup.9 Φ.sub.9.sup.26.

Assume for the moment that:

    (α.sub.0  γ.sub.0)κ.sub.1  Ω.sub.3 to 1 β.sub.0 (α.sub.0  γ.sub.0) (λ.sub.1 λ.sub.cc1 +λ.sub.cc1 ν+λ.sub.1 λ.sub.cc1 ν)

can be generated by the fourth stage. Let this value be designated as X₈. In addition, assume that λ₁ ν can be generated by the fourth stage and let it be designated by X_(d). That these conditions are true will be shown in the stage-by-stage implementation to follow. With these assumptions, OF can be calculated as:

    OF=X.sub.8  X.sub.d (T.sub.1 G.sub.1.sup.*8 +T.sub.1 T.sub.2.sup.9 Φ.sub.9.sup.26).

By distributing X_(d) this expression becomes:

    OF=X.sub.8  (X.sub.d T.sub.1 G.sub.1.sup.*8 +X.sub.d T.sub.1 T.sub.2.sup.9 Φ.sub.9.sup.26).

Let

    X.sub.6 =X.sub.d T.sub.1

    X.sub.9 =X.sub.d T.sub.1 T.sub.2.sup.9,

then,

    OF=X.sub.8  (X.sub.6 G.sub.1.sup.*8 +X.sub.9 Φ.sub.9.sup.26).

This expression can be developed by expanding the EXCLUSIVE-OR and applying Boolean identities as follows. ##EQU37##

This expression is implementable in the fifth stage if X₆ +G₁ ^(*8), X₆, X₉, and X₈ can be generated by the fourth stage. The other values were shown to be implementable by the fourth stage in "Carry Extraction for the Second Implementation Scheme".

First, consider the generation of X₆ which is: ##EQU38##

But ν is:

    ν=Ω.sub.4 σ.sub.0 +L.sub.0.

Since Ω₄ is a control signal input to the ALU and σ₀ and L₀ are both calculated in the first stage of the ALU, then ν can be calculated in the second stage. Also, T₁ as well as λ₁ were shown previously to be calculable by the second stage. Therefore, X₆ can be calculated in the third stage by: ##EQU39##

X₉ which is X₆ T₂ ⁹ is calculable in the fourth stage since X₆ and T₂ ⁹ are calculated in the third stage.

Next consider the generation of X₆ +G₁ ^(*8). The generation of G₁ ^(*8) has been discussed previously. Making use of these results and denoting X₆ +G₁ ^(*8) as X₁₀ gives: ##EQU40##

All of the values in this expression have been shown previously to be calculable in three stages; therefore, X₁₀ can be calculated in the fourth stage.

To show that OF can be generated in five stages, it remains to show that X₈ can be generated in four stages. The four stage generation of X₈ is as follows:

STAGE 1

    X.sub.1 =α.sub.0  γ.sub.0

    X.sub.2 =(α.sub.0  γ.sub.0)

STAGE 2 ##EQU41##

STAGE 3 ##EQU42##

STAGE 4 ##EQU43##

In this presentation, the calculation of κ₁ that occurs in stage 3 was omitted since it has been shown earlier how this occurs. With the above values, OF can be calculated in the fifth stage as:

STAGE 5

    OF=X.sub.8 X.sub.9 X.sub.10 +X.sub.8 X.sub.6 G.sub.1.sup.*8 +X.sub.8 X.sub.9 Φ.sub.9.sup.26 +X.sub.8 X.sub.10 Φ.sub.9.sup.26.

The logic diagram for generating overflow for the second implementation scheme is shown in FIG. 5.

Result Equal Zero Determination

The detection of result equal zero consists of two pads. The first pad is the actual determination that Λ_(i), the ALU output, for 0≦i≦31 is zero for each and every i. This determination will be denoted by R₌₀. The second part is the qualification of R₌₀ to account for overflow conditions. The method of detecting R₌₀ depends upon whether or not the ALU supports the collapsing of interlocks between two instructions in which both specify an ALU operation with the second specifying a logical operation. If collapsing of such interlocks is supported, case 1, the detection of R₌₀ is direct from the result. If the collapsing of such interlocks is not supported, case 2, R₌₀ can be predicted; thereby, allowing the determination of R₌₀ earlier in the execution cycle.

For case 1, the determination of R₌₀ is performed directly on the results from the ALU. Λ_(i). This output has been shown to be obtainable in five stages (U.S. Ser. No. 504,910, supra.). The result is zero if each and every bit of the results zero. This can be expressed as:

    R.sub.=0 =Λ.sub.0 Λ.sub.1 Λ.sub.2 . . . Λ.sub.31,

a 32-way AND between all of the inverted ALU output bits. This expression can be implemented in two stages with an eight-way AND gate followed by a four-way AND gate. Alternatively, R₌₀ can be expressed as:

    R.sub.=0 =(Λ.sub.0 + . . . +Λ.sub.7)(Λ.sub.8 + . . . +Λ.sub.15)(Λ.sub.16 + . . . +Λ.sub.23)(Λ.sub.24 + . . . +Λ.sub.31).

Expressing R₌₀ in this manner allows its generation by eight-way OI gates followed by a four-way AND gate and avoids the requirement of the generation of the one's complement of the result, Λ_(i). In either case, R₌₀ can be generated in seven stages with the assumed bookset since the result can be generated in five.

As mentioned above, if the collapsing of particular interlocks is not supported in the ALU the detection of R₌₀ can be predicted. A development of such a prediction scheme for the three-to-one ALU follows.

The functions required in the ALU can be divided into four categories (see U.S. Ser. No. 07/504,910, and Phillips, et al. supra.) These categories are:

    ______________________________________                                         A+B+Γ    Arithmetic followed by Arithmetic                               B+(A LOP Γ)                                                                             Logical followed by Arithmetic                                  B LOP (A+Γ)                                                                             Arithmetic followed by Logical                                  B LOP (A LOP Γ)                                                                         Logical followed by Logical.                                    ______________________________________                                    

Two of these categories, three and four, occur when interlocks are collapsed between two instructions which both specify an ALU operation with the second instruction specifying a logical operation. In these categories, the output of the adder is modified by a logical operation. No method is known for generating R₌₀ early for these conditions. Therefore, if the early generation of R₌₀ is desired, collapsing of interlocks between instruction sequences in which these functions arise can not be supported by the ALU. These instructions sequences must be issued and executed serially. As a result, only the functions contained in the first two categories of the above list need to be considered when considering the early generation of R₌₀. In the following, the early prediction scheme is first applied to the first category in which a three-to-one addition is executed. These results will then be extended to cover the second category contained in the above list.

Implied in three-to-one addition given in the first category are the addition of two operands and subtraction of a third operand, the subtraction of two operands from a third operand as well as the addition of three operands. These functions can be represented as:

    A+B+Γ

    A+B-Γ

    A-B+Γ

    A-B-Γ

in which + represents addition, - represents subtraction and A, B, and Γ are the three operands. By representing each operand as a two's complement number, these functions can be rewritten as:

    A+B+Γ

    A+B+(Γ+1)

    A+(B+1)+Γ

    A+(B+1)+(Γ+1)

or,

    A+B+Γ

    A+B+Γ+1

    A+B+1+Γ

    A+B+1+Γ+1.

By using the notation B* to denote either the operand or the one's complement of the operand as required by the operation to be performed, these functions can be expressed as:

    A+B*+Γ*+τ.sub.2 +τ.sub.1

where τ₂ and τ₁ are either 0 or 1 as required by the operation. By the additive identity, this expression is equivalent to:

    A+B*+Γ*+τ.sub.2 -1 +τ.sub.1 +1.

The first three terms of the expression:

    A+B*+Γ*

can be considered as a three-to-two addition represented as: ##EQU44##

Since τ₂ is either 1 or 0, it can be expressed as:

    0 0 . . . τ.sub.2.

Therefore, since the carry, λ, is shifted one bit to the left before being added to the sum, σ, τ₂ can be added to the carry as: ##EQU45##

Using this result, the expression A+B*+Γ*+τ₂ can be generated as: ##EQU46##

In two's complement notation, a negative one is represented as a string of one's, i.e. as:

    1 1 . . . 1.

Thus, A+B*+Γ*+τ₂ -1 can be expressed as a series of two three-to-two additions as: ##EQU47## thereby producing two variables P_(x) and P_(y).

Since the two's complement representation for τ₁ is:

    0 0 . . . τ.sub.1,

A+B*+Γ*+τ₂ -1 +τ₁ can be computed by P_(x) +P_(y) +τ₁. P_(y) and τ₁ can be added in a manner similar to that in which λ and T₂ were added to give: ##EQU48##

Thus, the ultimate result from the three-to-one addition can be produced by the two-to-one addition of P_(x) and (P_(y) +τ₁ ). This addition can be represented as: ##EQU49## where S is the ultimate result of the operation A+B*+Γ*+τ₂ +τ₁ -1. For this two-to-one addition, 1 is supplied as the carry in. The ultimate result is zero if S_(i), is 0 for all 0≦i≦31.

The generation of the ultimate result, A+B*+Γ*+τ₂ +τ₁ +1-1, as described above can be summarized as follows: ##EQU50##

The advantages of representing the three-to-one addition operations in the fashion just described should be come evident in the discussions to follow.

The advantages of the above representation result from the theorems to follow. For simplicity of exposition, let P_(y).sbsb.32 =τ₁ and let P_(x).sbsb.0 P_(x).sbsb.1 . . . P_(x).sbsb.31 be denoted by P_(x) and P_(y).sbsb.1 P_(y).sbsb.2 . . . P_(y).sbsb.31 P_(y).sbsb.32 be denoted by P_(y).

Theorem 1:

If S_(i) =0, then the carry at position i, φ₁, generated by the addition of P_(x), P_(y) and 1 is equal to 1 for all 0≦i≦31.

Proof:

Theorem 1 can be proven by induction.

Base of induction

The expression for the sum at bit position 31 is: ##EQU51##

Assuming that S₃₁ =0, then

    P.sub.x.sbsb.31  P.sub.y.sbsb.32 0,

therefore,

    P.sub.x.sbsb.31  P.sub.y.sbsb.32 =1.

The carry produced at bit position 31, φ₃₁, is:

    φ.sub.31 =P.sub.x.sbsb.31 P.sub.y.sbsb.32 +P.sub.x.sbsb.31 (1)+P.sub.y.sbsb.32 (1)

where+ represents logical OR. This reduces to:

    φ.sub.31 =P.sub.x.sbsb.31 +P.sub.y.sbsb.32.

Since if S₃₁ =0

    P.sub.x.sbsb.31  P.sub.y.sbsb.32 =1,

and since the EXCLUSIVE-OR is one if one or the other of P_(x).sbsb.31 , or P_(y).sbsb.32 is one, but not both, then:

    P.sub.x.sbsb.31 +P.sub.y.sbsb.32 =1

so that,

    φ.sub.31 =1.

Consequently, the carry from bit 31 into bit 30 is guaranteed to be a one if the sum of the addition at bit 31, S₃₁, is equal to zero.

Step of induction

Assume that S_(i) =0 and φ_(i+1) =1. Since the sum at i, S_(i), is

    S.sub.i =P.sub.x.sbsb.i  P.sub.y.sbsb.i+1  φ.sub.i+1,

then

    P.sub.x.sbsb.i  P.sub.y.sbsb.i+1  1=0,

or,

    P.sub.x.sbsb.i  P.sub.y.sbsb.i+1 =0

    P.sub.x.sbsb.i  P.sub.y.sbsb.i+1 =1.

The carry at i is:

ti φ_(i) =P_(x).sbsb.i P_(y).sbsb.i+1 +P_(x).sbsb.1 P_(y).sbsb.i+1 φ_(i+1).

Since φ_(i+1) =1, then ##EQU52##

But from above,

    P.sub.x.sbsb.i  P.sub.y.sbsb.i+1 =1,

from which it follows that

    P.sub.x.sbsb.i +P.sub.y.sbsb.i+1 =1,

and,

    φ.sub.i =1.

From steps one and two above, it follows by mathematical induction that φ_(i) =1for 0≦i≦31.

QED

Theorem 2:

The sum, S, is zero if P_(x).sbsb.i P_(y).sbsb.i+1 =1 for 0≦i≦31.

Proof:

Proof of if

If S=0 then from Theorem 1, φ_(i+1) =1 for any i from which it follows that:

    P.sub.x.sbsb.i  P.sub.y.sbsb.i+1 =1.

since S_(i) is zero.

Proof of only if

Consider the carry generated at φ_(i). This carry is: ##EQU53##

Since by assumption,

    P.sub.x.sbsb.i  P.sub.y.sbsb.i+1 =1,

then

    φ.sub.i =φ.sub.i+1

Since this must hold for all i and since the carry in is 1, then

    φ.sub.i =φ.sub.i+1 = . . . =1

Let S_(i) =1. But S_(i) is:

    S.sub.i =P.sub.x.sbsb.i  P.sub.y.sbsb.i+1  φ.sub.i+1.

However,

    P.sub.x.sbsb.i  P.sub.y.sbsb.i+1 =1

from which it follows that:

    φ.sub.i+1 =0.

Therefore, the assumption that S_(i) =1 leads to a contradiction and is therefore erroneous. Thus, S_(i) must be zero.

QED

The conditions for the result of a three-to-one add type operation to be zero follow from Theorem 1 and Theorem 2. These conditions are:

    P.sub.x.sbsb.31  τ.sub.1 =1

and

    P.sub.x.sbsb.i  P.sub.y.sbsb.i+1 =1

for all 0≦i≦30. Result equal zero, denoted as R₌₀, can therefore be determined from:

    R.sub.=0 =(P.sub.x.sbsb.0  P.sub.y.sbsb.1)(P.sub.x.sbsb.1  P.sub.y.sbsb.2) . . . (P.sub.x.sbsb.30  P.sub.y.sbsb.31)(P.sub.x.sbsb.31  τ.sub.1).

These results need to be extended to allow R₌₀ to be produced for interlocked instruction sequences in which a logical instruction is compounded with an arithmetic instruction. This case produces the second category shown earlier. Three implementations have been proposed for producing the desired results from the ALU provided by the Phillips application, supra. The application the above mechanism for generating result equal zero to the second function category is impacted by the choice of implementation. In particular, the generation of result equal zero depends on what outputs are generated by the CSA and by the logic function block in the ALU. Since two of the three implementations found in the Phillips application, supra. produce identical CSA and logic function block outputs while the third produces a unique set of outputs, the implementations can be divided into two implementation schemes for discussing the generation of R₌₀ as was done for the discussion of overflow. The application of the mechanism for generating result equal zero to these two schemes is discussed in the following. Along with the discussion, a stage by stage description of the mechanism is presented.

In the first implementation scheme, an unmodified three-to-two CSA is used to generate a sum, σ, and a carry, λ. The inputs to the CSA, however, are controlled so that when executing the second functional category, the sum is equal to the second operand and the carry is zero. In parallel, the logic function block generates the desired logical operation. The first input to the two-to-one adder at bit position i is the CSA sum, σ, while the second input at the same position is derived by ORing the carry from the CSA at bit position i+1, λ_(i+1), with the output from the logic function block at bit position i, L_(i), for all i between 0 and 30. At bit position 31, the first input is σ₃₁ while the second is τ₂ ORed with L₃₁ where τ₂ is one of the hot one's supplied to the ALU. These results imply that the result equal zero scheme derived above can be modified to include the second functional category for the ALU implementation being considered by replacing λ_(i+1) with λ_(i+1) +L_(i) for all 0≦i≦30 where + indicates the OR function, when generating P_(x).sbsb.i and P_(y).sbsb.i.

With these modifications, the stage by stage implementation of result equal zero is as follows. In the first stage, the CSA sum, σ, the CSA carry, λ, and the output of the logic function block are generated. In the expressions that follow, the inputs to the CSA are denoted by the lower case greek letters corresponding to the appropriate ALU input. This is done to distinguish the controlled CSA input, which may be forced to 0, from the corresponding ALU input. For a three-to-one addition, the ALU input would be passed to the CSA, for example, α_(i) would be equal to A_(i). For the addition of the result from a logical operation with a third ALU input, however, α_(i) and γ_(i) are forced to zero. With this notation, the results from the first stage are:

    σ.sub.i =α.sub.i  β.sub.i  γ.sub.i

    λ.sub.i =α.sub.i β.sub.i +α.sub.i γ.sub.i +β.sub.i γ.sub.i

    L.sub.i =A.sub.i Ω.sub.OALASL +Γ.sub.i Ω.sub.OALASL +A.sub.i Γ.sub.i Ω.sub.XAAL +A.sub.i Γ.sub.i Ω.sub.XOSL

in which Ω_(OALASL), Ω_(XAAL), and Ω_(XOSL) represent control signals supplied to the ALU. The details of this implementation can be found in U.S. Pat. No. 5,299,319 Phillips, supra. which has been incorporated hereby by reference. In the next stage, P_(x) and P_(y) are generated as the three-to-two addition of the CSA sum with the CSA carry or τ₂ ORed with the logic block output as discussed above, and with minus one. The results are: ##EQU54##

These expressions can be simplified by recognizing that:

    X 1=X

    X(1)=X

    XY+X+Y=X+Y

to give: ##EQU55##

The expressions for P_(x).sbsb.i and P_(x).sbsb.31 are not implementable in one stage with the assumed bookset. They, however, can be written as: ##EQU56## and,

    P.sub.x.sbsb.31 =σ.sub.31 (τ.sub.2 +L.sub.31)+σ.sub.31 (τ.sub.2 +L.sub.31)

    P.sub.x.sbsb.31 =σ.sub.31 τ.sub.2 +σ.sub.31 L.sub.31 +σ.sub.31 τ.sub.2 L.sub.31

both of which can be implemented in one stage with the assumed bookset.

In the third stage, the two way XOR's can be generated in preparation of generating R₌₀. The desired XOR's are: ##EQU57##

In stage four, eight-way ANDs can be applied to these signals to begin producing a single result equal zero signal. The desired expressions are:

    R.sub.=0 (0:7)=R.sub.=0 (0)R.sub.=0 (1) . . . R.sub.=0 (7)

    R.sub.=0 (8:15)=R.sub.=0 (8)R.sub.=0 (9) . . . R.sub.=0 (15)

    R.sub.=0 (16:23)=R.sub.=0 (16)R.sub.=0 (17) . . . R.sub.=0 (23)

    R.sub.=0 (24:31)=R.sub.=0 (24)R.sub.=0 (25) . . . R.sub.=0 (31).

Finally, the desired signal, R₌₀, is produced in the fifth stage with a four-way AND by:

    R.sub.=0 =R.sub.=0 (0:7)R.sub.=0 (8:15)R.sub.=0 (16:23)R.sub.=0 (24:31).

The logic diagram for the generation for result equal to zero is shown in FIG. 6.

In the second implementation scheme, the CSA and the logic function block are implemented according to U.S. Pat. No. 5,299,319, Phillips, supra. so that the outputs are:

    σ.sub.i =α.sub.i  β.sub.i γ.sub.i

    0≦i≦31

    λ.sub.0 =α.sub.0 β.sub.0 Ω.sub.1 +α.sub.0 γ.sub.0 Ω.sub.2 +β.sub.0 γ.sub.0 Ω.sub.1

    λ.sub.i =α.sub.i β.sub.i Ω.sub.1 +α.sub.i γ.sub.i Ω.sub.2 +β.sub.i γ.sub.i Ω.sub.1 +β.sub.i-1 Ω.sub.3

    1≦i≦31

    λ.sub.32 =τ.sub.2 Ω.sub.3 +β.sub.31 Ω.sub.3

    L.sub.i =A.sub.i Ω.sub.OALASL +Γ.sub.i Ω.sub.OALASL +A.sub.i Γ.sub.i Ω.sub.XAAL +A.sub.i Γ.sub.i Ω.sub.XAAL

    0≦i≦31.

In these expressions, the notation is as defined above with the addition of Ω₁, Ω₂, and Ω₃ which are controls signals supplied to the ALU. The inputs to the two-to-one CLA, however, are derived differently than in the first implementation scheme. In this case, the first input to the CLA at bit position i is λ_(i+1) for 0≦i≦31. The second input, however, at bit position i can be expressed by the following Boolean expression:

    Ω.sub.4 σ.sub.i +L.sub.i

where Ω₄ is a control signal supplied to the ALU and 0≦i≦31. Thus, for these outputs, the result equal zero scheme can be modified to include the second functional category for the ALU implementation by replacing σ_(i) with Ω₄ σ_(i) +L_(i).

With these modifications, the generation of R₌₀ proceeds as follows. In the first stage,

    σ.sub.i =α.sub.i  β.sub.i  γ.sub.i

    0≦i≦31

    γ.sub.0 =α.sub.0 β.sub.0 Ω.sub.1 +α.sub.0 γ.sub.0 Ω.sub.2 +β.sub.0 γ.sub.0 Ω.sub.1

    γ.sub.i =α.sub.i β.sub.i Ω.sub.1 +α.sub.i γ.sub.i Ω.sub.2 +β.sub.i γ.sub.i Ω.sub.1 +β.sub.i-1 Ω.sub.3

    1≦i≦31

    γ.sub.32 =τ.sub.2 Ω.sub.3 +β.sub.31 Ω.sub.3

    L.sub.i =A.sub.i Ω.sub.OALASL +Γ.sub.i Ω.sub.OALASL +A.sub.i Γ.sub.i Ω.sub.XAAL +A.sub.i Γ.sub.i Ω.sub.XAAL

    0≦i≦31

can be generated. As before, the details of this implementation can be found in EN9-91-005, Phillips, supra. The generation of P_(x) and P_(y) can proceed in the second stage. These signals are generated by:

    P.sub.x.sbsb.i =(Ω.sub.4 σ.sub.i +L.sub.i) λ.sub.i+1  1

    P.sub.y.sbsb.i =(Ω.sub.4 σ.sub.i +L.sub.i)λ.sub.i+1 +(Ω.sub.4 σ.sub.i +L.sub.i)(1)+λ.sub.i+1 (1)

for all i such that 0≦i≦31. Simplification of these expressions results in:

    P.sub.x.sbsb.i =(Ω.sub.4 σ.sub.i +L.sub.i) λ.sub.i+1

    P.sub.y.sbsb.i =Ω.sub.4 σ.sub.i +L.sub.i +λ.sub.i+1.

The expression for P_(x) is not implementable in one stage as expressed, but the expression can be rewritten as: ##EQU58## which is implementable in one stage with the assumed bookset. The remainder of the generation of R₌₀ consisting of the third, fourth, and fifth stages can be achieved with the identical circuitry as used for the first implementation scheme. Thus, R₌₀ can be obtained in the fifth stage which is the same stage that the output of the ALU is generated, see U.S. Pat. No. 5,299,319, Phillips, supra.

Clearly, the inventions we have described by way of exemplary implementation schemes or preferred embodiments and in illustration of our best mode for practicing the inventions provide a basis for potential growth in processor performance. Accordingly, it will be understood that those skilled in the art after reviewing our presently contemplated implementations for practicing our inventions, both now and in the future, will envision further improvements and enhancements which may even amount to inventions, and these should be understood to be within the intended s cope of the following claims which should be construed to maintain the first inventors' rights as they should be accorded. 

What is claimed is:
 1. An ALU status determination apparatus comprising:a three-to-one ALU means for executing plural instructions in parallel, including first and second instructions of a pair of instructions; predicting means for predicting the status of three-to-one ALU operations, said status being indicative of (a) the presence or absence of carries generated by said three-to-one ALU means and (b) whether or not said second instruction of the pair of instructions is independent or dependent upon the result of the operation of said first instruction; and overflow means for predicting an overflow and the carries required to compute the overflow computed by: ##EQU59##
 2. The apparatus according to claim 1 wherein an overflow means is provided for predicting an overflow for arithmetic followed by arithmetic operations in the said three-to-one ALU means.
 3. The apparatus according to claim 2 wherein the arithmetic operations are additions and subtractions in two's complement or unsigned form.
 4. The apparatus according to claim 1 wherein overflow means is provided for predicting the overflow for logical followed by arithmetic operations in said three-to-one ALU means.
 5. The apparatus according to claim 4 wherein the arithmetic operations are additions and substractions in two's complement or unsigned form and the logical operations include AND, OR, or XOR.
 6. The apparatus according to claim 1 wherein carries are computed in five stages by computing:STAGE 1 ##EQU60## STAGE 2 ##EQU61## STAGE 3 ##EQU62## STAGE 4

    κ.sub.  *=κ.sub.0  λ.sub.0

    κ.sub.1 *=κ.sub.1  λ.sub.1

    φ.sub.1 =T.sub.1 G.sub.1.sub.*8 +T.sub.1 T.sub.2.sup.9 G.sub.9 *.sup.16 T.sub.1 T.sub.2.sup.17 G.sub.17 *.sup.24 +T.sub.1 T.sub.2.sup.25 Φ.sub.25.sup.31

STAGE 5

    C.sub.1 =κ.sub.1 * φ.sub.1

    C.sub.0 =κ.sub.0 *T.sub.0 +κ.sub.0 *G.sub.0 φ.sub.1 +κ.sub.0 *G.sub.0 +κ.sub.0 *T.sub.0 φ.sub.1.


7. The apparatus according to claim 1 wherein overflow is computed from the carries of claim 6 as:

    OF=X.sub.6  X.sub.4 φ.sub.1 =X.sub.6 X.sub.4 φ.sub.1 +X.sub.6 X.sub.4 +X.sub.6 φ.sub.1.

where

    X.sub.1 =α.sub.0  γ.sub.0

    X.sub.2 =β.sub.0 (α.sub.0  γ.sub.0)=β.sub.0 α.sub.0 γ.sub.0 +β.sub.0 α.sub.0 γ.sub.0

    X.sub.3 =σ.sub.0 λ.sub.1 +σ.sub.0 L.sub.0

    X.sub.4 =σ.sub.0 L.sub.0 λ.sub.1 +σ.sub.0 λ.sub.1 +σ.sub.0 L.sub.0

    X.sub.5 =X.sub.2  X.sub.3

    κ.sub.1 =T.sub.cc1 G.sub.cc1.sup.*7 +T.sub.cc1.sup.8 G.sub.CC8.sup.*15 +T.sub.cc1.sup.16 G.sub.cc16.sup.*23 +T.sub.cc1.sup.24 Ψ.sub.24.sup.30

    X.sub.6 =X.sub.5  X.sub.1 κ.sub.1 =X.sub.5 X.sub.1 +X.sub.5 κ.sub.1 +X.sub.5 X.sub.1 κ.sub.1

    φ.sub.1 =T.sub.1 G.sub.1.sup.*8 +T.sub.1 T.sub.2.sup.9 G.sub.9.sup.*16 +T.sub.1 T.sub.2.sup.17 G.sub.17.sup.*24

     +T.sub.1 T.sub.2.sup.25 Φ.sub.25.sup.31.


8. The apparatus according to claim 1 wherein the overflow is computed in five stages by:STAGE 1

    X.sub.1 =α.sub.0  γ.sub.0

    X.sub.2 =β.sub.0 (α.sub.0  γ.sub.0)=β.sub.0 α.sub.0 γ.sub.0 +β.sub.0 α.sub.0 γ.sub.0

STAGE 2

    X.sub.3 =σ.sub.0 λ.sub.1 +σ.sub.0 L.sub.0

    X.sub.4 =σ.sub.0 L.sub.0 λ.sub.1 +σ.sub.0 λ.sub.1 +σ.sub.0 L.sub.0

STAGE 3

    X.sub.5 =X.sub.2  X.sub.3

    κ.sub.1 =T.sub.cc1 G.sub.cc1.sup.*7 +T.sub.cc1.sup.8 G.sub.cc8.sup.*15 +T.sub.cc1.sup.16 G.sub.cc16.sup.*23 +T.sub.cc1.sup.24 Ψ.sub.24.sup.30

STAGE 4

    X.sub.6 =X.sub.5  X.sub.1 κ.sub.1 =X.sub.5 X.sub.1 +X.sub.5 κ.sub.1 +X.sub.5 X.sub.1 κ.sub.1

    φ.sub.1 =T.sub.1 G.sub.1.sup.*8 +T.sub.1 T.sub.2.sup.9 G.sub.9.sup.*16 +T.sub.1 T.sub.2.sup.17 G.sub.17.sup.*24

     +T.sub.1 T.sub.2.sup.25 Φ.sub.25.sup.31

STAGE 5

    OF=X.sub.6  X.sub.4 φ.sub.1 =X.sub.6 X.sub.4 φ.sub.1 +X.sub.6 X.sub.4 +X.sub.6 φ.sub.1.


9. An ALU status determination apparatus according to claim 1 wherein said predicting means include zero means for predicting a result equal zero in said three-to-one ALU means.
 10. The apparatus according to claim 9 wherein said zero means predicts the result equal zero for arithmetic followed by arithmetic operations in said three-to-one ALU means.
 11. The apparatus according to claim 10 wherein the the arithmetic operations are additions and subtractions in two's complement or unsigned form.
 12. The apparatus according to claim 9 wherein said zero means predicts the result equal zero for logical followed by arithmetic operations in said three-to-one ALU means.
 13. The apparatus according to claim 12 wherein the arithmetic operations are additions and subtractions in two's complement or unsigned form and logical operations are binary AND, OR, or XOR.
 14. An ALU status determination apparatus comprising:a three-to-one ALU means for executing plural instructions in parallel, including first and second instructions of a pair of instructions; predicting means for predicting the status of three-to-one ALU operations, said status being indicative of (a) the presence or absence of carries generated by said three-to-one ALU means and (b) whether or not said second instruction of the pair of instructions is independent or dependent upon the result of the operation of said first instruction; and overflow means and the carries required to compute the overflow computed by: ##EQU63##
 15. The apparatus according to claim 14 wherein the carries computed for overflow in claim 14 are computed in five stages by computing:STAGE 1 ##EQU64## STAGE 2 ##EQU65## STAGE 3 ##EQU66## STAGE 4

    κ.sub.  *=κ.sub.0  λ.sub.cc0

    κ.sub.1 *=κ.sub.1  λ.sub.cc1

    G.sub.1.sup.*8 =G.sub.1.sup.*2 +T.sub.2.sup.3 G.sub.3.sup.*8

    G.sub.1.sup.*8 =G.sub.1.sup.*2 T.sub.2.sup.3 +G.sub.1.sup.*2 G.sub.3.sup.*8

    U.sub.2 =T.sub.1 +T.sub.2.sup.3 G.sub.1.sup.*2 +T.sub.2.sup.9 G.sub.1.sup.*2 G.sub.3.sup.*8

    U.sub.3 =G.sub.0 *+T.sub.0.sup.1 G.sub.1.sup.*2 +T.sub.0.sup.1 T.sub.2.sup.3 G.sub.3.sup.*8

    U.sub.4 =T.sub.0 +G.sub.0 *T.sub.1 +T.sub.2.sup.3 U.sub.1 +T.sub.2.sup.9 U.sub.1 G.sub.3.sup.*8

    Φ.sub.9.sup.26 =G.sub.9.sup.*14 +T.sub.10.sup.11 T.sub.12.sup.15 G.sub.15.sup.*20 +T.sub.10.sup.11 T.sub.12.sup.21 G.sub.21.sup.*26 +T.sub.10.sup.11 T.sub.12.sup.27 Φ.sub.27.sup.31

STAGE 5

    c.sub.1 =κ.sub.1 *U.sub.2 +κ.sub.1 *T.sub.1 G.sub.1.sup.*8 +κ.sub.1 *T.sub.1.sup.9 Φ.sub.9.sup.26 +κ.sub.1 *G.sub.1.sup.*8 Φ.sub.9.sup.26

    c.sub.0 =κ.sub.0 *U.sub.4 +κ.sub.0 *U.sub.1 Φ.sub.9.sup.26 +κ.sub.0 *T.sub.0.sup.9 Φ.sub.9.sup.26.


16. The apparatus according to claim 14 wherein there is a computation of overflow from the carries by:

    OF=X.sub.8 X.sub.9 X.sub.10 +X.sub.8 X.sub.6 G.sub.1.sup.*8 +X.sub.8 X.sub.9 Φ.sub.9.sup.26 +X.sub.8 X.sub.10 Φ.sub.9.sup.26

where ##EQU67##
 17. The apparatus according to claim 14 wherein there is a calculation in five stages of overflow from the carries by:STAGE 1

    X.sub.1 =α.sub.0  γ.sub.0

    X.sub.2 =(α.sub.0  γ.sub.0

STAGE 2 ##EQU68## STAGE 3 ##EQU69## STAGE 4 ##EQU70## and where a calculation of κ₁ occurs in Stage 3, and where with the above values, OF is calculated in the fifth stage as: STAGE 5

    OF=X.sub.8 X.sub.9 X.sub.10 +X.sub.8 X.sub.6 G.sub.1.sup.*8 +X.sub.8 X.sub.9 Φ.sub.9.sup.26 +X.sub.8 X.sub.10 Φ.sub.9.sup.26.


18. An ALU status determination apparatus comprising:a three-to-one ALU means for executing plural instructions including a three-to-one binary adder including a carry save adder (CSA) and a 2-1 adder having operands denoted as A, B, and Γ; and a logical operation block means for feeding said 2-1 adder; and said 2-1 adder having two of three possible inputs and having a set and suppress means for selecting two of the three inputs as the input for the operand by setting or suppressing the operand; and zero means for predicting a result equal zero outcome in the execution of an instruction by said three-to-one ALU means; and wherein said zero means predicts operations by: ##EQU71## representing the computation of A+B*+Γ*+τ₂ +τ₁ +1-1, to compute the worse case scenario of addition subtractions in arithmetic followed by arithmetic operations, said operations being expressed by

    A+B+Γ

    A+B+(Γ+1)

    A+(B+1)+Γ

    A+(B+1)+(Γ+1)

or,

    A+B+Γ

    A+B+Γ+1

    A+B+1 +Γ

    A+B+1 +Γ+1.


19. The apparatus according to claim 18 wherein to compute the result equal zero for claim 18 three operands are provided to the three-to-one binary adder, and said logical operation block means has operands set or suppressed in order to compute properly an arithmetic operation followed by an arithmetic operation and a logical operation followed by an arithmetic operation.
 20. The apparatus according to claim 18 wherein said zero means of said apparatus operates in parallel with the CSA, the 2-1 adder and the logical block means and predicts the result equal zero outcome.
 21. The apparatus of claim 18 wherein either an operand itself or the one's complement of that operand is used in the execution of the three-to-one ALU instruction as required by the operation being performed.
 22. An ALU status determination apparatus, comprising:a three-to-one ALU means for executing plural instructions including a three-to-one binary adder including a carry save adder (CSA) and a 2-1 adder having operands denoted as A, B, and Γ; and a logical operation block means for feeding said 2-1 adder; and said 2-1 adder having two of three possible inputs and having a set and suppress means for selecting two of the three inputs as the input for the operand by setting or suppressing the operand; and zero means for predicting a result equal zero outcome in the execution of an instruction by said three-to-one ALU means; and wherein the result equal zero is computed by:

    R.sub.=0 =(P.sub.x.sbsb.0  P.sub.y.sbsb.1)(P.sub.x.sbsb.1  P.sub.y.sbsb.2) . . . (P.sub.x.sbsb.30  P.sub.y.sbsb.31) (P.sub.x.sbsb.31  τ.sub.1).

where: ##EQU72##
 23. An ALU status determination apparatus, comprising:a three-to-one ALU means for executing plural instructions including a three-to-one binary adder including a carry save adder (CSA) and a 2-1 adder having operands denoted as A, B, and Γ; a logical operation block means for feeding said 2-1 adder; said 2-1 adder having two of three possible inputs and having a set and suppress means for selecting two of the three inputs as the input for the operand by setting or suppressing the operand; and zero means for predicting a result equal zero outcome in the execution of an instruction by said three-to-one ALU means; and wherein the result equal zero is computed in five logic stages by: STAGE 1 ##EQU73## STAGE 2 ##EQU74## STAGE 3 ##EQU75## STAGE 4

    R.sub.=0 (0:7)=R.sub.=0 (0)R.sub.=0 (1) . . . R.sub.=0 (7)

    R.sub.=0 (8:15)=R.sub.=0 (8)R.sub.=0 (9) . . . R.sub.=0 (15)

    R.sub.=0 (16:23)=R.sub.=0 (16)R.sub.=0 (17) . . . R.sub.=0 (23)

    R.sub.=0 (24:31)=R.sub.=0 (24)R.sub.=0 (25) . . . R.sub.=0 (31)

STAGE 5

    R.sub.=0 =R.sub.=0 (0:7)R.sub.=0 (8:15)R.sub.=0 (16:23)R.sub.=0 (24:31).


24. An ALU status determination apparatus, comprising:a three-to-one ALU means for executing plural instructions including a three-to-one binary adder including a carry save adder (CSA) and a 2-1 adder having operands denoted as A, B, and Γ; and a logical operation block means for feeding said 2-1 adder; and zero means for predicting a result equal zero outcome in the execution of an instruction by said three-to-one ALU means; and wherein A and Γ are equal to zero for the CSA when computing a logical followed by arithmetic operation and wherein one of two inputs of the 2-1 adder has the carry of the CSA suppressed allowing the result of the logical operation to pass through and having the inputs of the CSA equal to the operands for arithmetic followed by arithmetic when one of the inputs in the 2-1 adder has suppressed a logical operand and allowed a carry of the CSA to pass through; and wherein said logical block means is in parallel with said three-to-one binary adder and computes the following:representing the computation of A+B*+Γ*+τ₂ +τ₁ +1-1, to compute the worse case scenario of addition subtractions in arithmetic followed by arithmetic operations as those operations are expressed by

    A+B+Γ

    A+B+(Γ+1)

    A+(B+1)+Γ

    A+(B+1)+(Γ+1)

or,

    A+B+Γ

    A+B+Γ+1

    A+B+1+Γ

    A+B+1+Γ+1. 